Systems and Methods of Sectioned Bit Line Memory Arrays, Including Hierarchical and/or Other Features

ABSTRACT

A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in some embodiments, the sectioned bit lines are arranged in hierarchical arrays. In other implementations, SRAM memory devices may be configured involving sectioned bit lines (including hierarchical) and a global bit line wherein the pass gates are configured to connect and isolate the sectioned bit line and the global bit line.

CROSS-REFERENCE TO RELATED APPLICATION INFORMATION

This is a continuation of application Ser. No. 14/091,290, filed Nov.26, 2013, published as US2014/0219011A1, now patent Ser. No. ______,which is a continuation (bypass) of application No. PCT/US12/68833,filed Dec. 10, 2012, published as WO2013/086538A1, and a continuation ofapplication Ser. No. 13/399,986, filed Feb. 17, 2012, published asUS2013/0148415A1, now U.S. Pat. No. 8,693,236, and acontinuation-in-part of application Ser. No. 13/316,391, filed Dec. 9,2011, published as US2013/0148414A1, now U.S. Pat. No. 8,593,860, all ofwhich are incorporated herein by reference in entirety.

BACKGROUND

1. Field

The innovations herein relate to static random access memory, and, moreparticularly, to systems and methods relating to SRAMs involvingsectioned bit lines in memory arrays, including embodiments arranged inhierarchical manner.

2. Description of Related Information

In high density static memory arrays, considerable effort is directedtowards minimizing bit line capacitance. Bit line capacitance affectsthe speed of memory cell sensing and overall stability of memory cells.One way to reduce bit line capacitance is to reduce memory cell size,which is sometimes feasible though is subject to technologicallimitations. By reducing the memory cell size, the bit line is shortenedbut the memory cell active current is also reduced. Consequently, theoverall performance of memory array may generally stay about the same.Performance may also be improved by reducing the number of memory cellson any given bit line. However, known practices in conventional SRAMsthat maintain sensing speed typically entail reducing memory arraysdensity, which yields larger array area(s). Overall, such existingsystems and methods suffer drawbacks relating to the failure to achievesmaller bit line capacitance in desired higher density memory arrays.

Other known systems and methods, such as with some DRAMs and folded bitline structures used in conventional DRAM, may include local bit lineconnected to gates of access transistors that pass representations ofthe local bit line onto a global bit line. However, such existingsystems and methods may have one or more of a variety of drawback, suchas being limited to having very small quantities of memory cells per bitline and thus very short bit lines due to their reduced sensingcapability. Voltage swings associated with the bit lines of such systemsand methods also tend to be large because of threshold voltage of gate.Further, such systems also suffer drawbacks related to the pass gatesbeing gate-connected the local bit line, to passing an inverse of thesignal on the local bit line, and/or to being pre-charged to highinstead of low.

Moreover, DRAM implementations and folded bit line structures used inthe conventional DRAM relate to a variety of disparate structural oroperational issues and/or restrictions. For one, bit lines are typicallycharged to half Vcc in DRAM. Further, for example, folded bit linestructures associated with conventional DRAMs are limited to two pairsof bit lines arranged on either side of the relevant sense amplifier.Also, due to the destructive nature of DRAM cell reading, various DRAMcells need to be sensed once a memory cell is turned on. Accordingly,there can only be one DRAM cell selected for every sense amplifier.Hence, as there can only be one memory cell selected on either the truebit line or the complement bit line, disparate issues associated withselecting memory cells on both at the same time are not present.Moreover, with DRAM, the word lines are not shared by the memory cellson the true bit line and complement bit line. In a hierarchical bit lineDRAM, for example, when one memory cell is selected on the true localbit line, there can be no memory cell selected on the complement localbit line at the same time. And no issues related to selection of passgates coupling the complement local bit lines and the complement globalbit lines are present, either. The complement global bit line, e.g., issimply used as a sensing reference in some cases. As such, among theother issues noted above, no design considerations relating to selectingmore than only the pass gate on the true local bit line areencountered/overcome.

In sum, as detailed in the innovations below, there is a need for thepresent systems and methods that may achieve smaller bit linecapacitance, improved memory cell stability and/or higher density memoryarrays.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which constitute a part of thisspecification, illustrate various implementations and features of thepresent inventions and, together with the description, help explainaspects of the innovations herein. In the drawings:

FIGS. 1A and 1B are diagrams of a 6-transistor (6T) memory cell and an8-transistor (8T) memory cell, respectively, as may be used inembodiment(s) of the innovations herein.

FIG. 1C is a diagram of a dual-port memory cell, as may be used inembodiment(s) of the innovations herein.

FIG. 2 is a diagram of an illustrative static random access memory(SRAM) including a sectioned bit line (SBL) and associated pass gatesaccording to a disclosed implementation.

FIG. 3 is a diagram of an illustrative SRAM including a plurality ofSBLs according to a disclosed implementation.

FIG. 4 is a diagram of an illustrative SRAM including an SBL andassociated read and write pass gates according to a disclosedimplementation.

FIG. 5 is a diagram of an illustrative SRAM including an SBL withillustrative pass gate circuitry as well as illustrative equalizationand/or write recovery circuitry according to a disclosed implementation.

FIG. 6 is a diagram of an illustrative SRAM including a plurality ofSBLs configured in a single row in the bit line direction with a senseamplifier according to a disclosed implementation.

FIG. 7 is a diagram of an illustrative SRAM including a plurality ofSBLs arranged in a matrix according to a disclosed implementation.

FIG. 8 is a diagram showing local connections of an illustrative matrixof a plurality of SBLs, such as that of FIG. 7, associated withexemplary SRAM memory according to a disclosed implementation.

FIG. 9A is a diagram of an SRAM without SBLs.

FIG. 9B is a diagram of an illustrative SRAM including a plurality ofSBLs according to a disclosed implementation.

FIG. 9C is a diagram of an illustrative SRAM including a plurality ofSBLs according to a disclosed implementation.

FIG. 10 is a diagram of an illustrative SRAM including an SBL withillustrative pass gate circuitry as well as illustrative equalizationand/or write recovery circuitry according to a disclosed implementation.

FIGS. 11 and 12 are diagrams of illustrative SRAMs including SBLs, 8Tmemory cells and associated read and write pass gates according todisclosed implementations.

FIGS. 13 and 14 are diagrams of illustrative SRAMs including SBLs,dual-port memory cells and associated read and write pass gatesaccording to disclosed implementations.

FIGS. 15A-15D are diagrams of illustrative SRAM cells including detailof exemplary layering of the SRAM structures according to disclosedimplementations.

FIG. 16 is a diagram of global bit lines with a local connection of SBLsaccording to disclosed implementations.

FIG. 17 is a diagram of global bit lines with multiple rows and columnsof SBLs according to disclosed implementations.

FIG. 18 is a diagram of a hierarchical column array of global bit lineswith local sense amplifiers and local data drivers according todisclosed implementations.

FIGS. 19A and 19B are diagrams illustrating local connectivity includingthe local sense amplifier and local data driver according to disclosedimplementations.

FIGS. 20A and 20B are diagrams of the local section bit line blockaccording to disclosed implementations.

FIG. 21 is a diagram of a global bit line with a sense amplifier andglobal data line driver according to disclosed implementations.

FIG. 22 is a diagram of a hierarchical column memory array according todisclosed implementations.

DETAILED DESCRIPTION OF ILLUSTRATIVE IMPLEMENTATIONS

Reference will now be made in detail to the innovations herein, examplesof which are illustrated in the accompanying drawings. Theimplementations set forth in the following description do not representall implementations consistent with the claimed invention. Instead, theyare merely some examples consistent with certain aspects related to thepresent innovations. Wherever possible, the same reference numbers willbe used throughout the drawings to refer to the same or like parts.

Systems and methods relating to a static random access memory (SRAM)including one or more sectioned bit lines (SBLs) are described. Aplurality of SBLs may be provided and may all be in communication with aglobal bit line (GBL). Each sectioned bit line may also be incommunication with one or more individual memory cells. Among otherthings, configurations consistent with the innovations herein mayprovide reduced bit line capacitance of the GBLs compared to priorconfigurations having the same number of memory cells.

Further, in some implementations, each of a plurality of memory cellsthat are associated with an SBL may connect onto true and complementlocal bit lines of the SBL. Each of the local bit lines may couple to apass gate that may act as a conductor and isolator of the SBL to theGBL.

FIGS. 1A and 1B are diagrams of a 6-transistor (6T) memory cell and an8-transistor (8T) memory cell, respectively, as may be used inembodiment(s) of the innovations herein. FIG. 1A is a diagram of a 6transistor (6T) memory cell 100 that is an example of a memory cell thatmay be used in exemplary SRAMs herein. Other memory cells havingdifferent numbers of transistors, different configurations, and/ordifferent components may be used, consistent with aspects of the presentinnovations. This example cell 100 may store a bit on four transistors110, 120, 130, 140 that form two inverters. Access transistors 150, 160may control access to the storage transistors 110, 120, 130, 140 duringa read or write operation. A wordline 170 may control the accesstransistors 150, 160 and thereby connect the cell 100 to the bit line180 and complement bit line 190. The bit lines 180, 190 may transferdata to and from the cell 100 during read and write operations. FIG. 1Bis a diagram of an 8 transistor (8T) memory cell that is another exampleof a memory cell that may be used in exemplary SRAMs herein. The 8Tmemory cell 101 of FIG. 1B may comprise the 6 transistors of FIG. 1A,arranged in similar manner, as well as two additional transistors 194,198 arranged in series between the read bit line and ground, wherein agate of the first additional transistor 194 may be coupled to the readwordline and a gate of the second additional transistor 198 may becoupled to the storage transistor(s), e.g., to a gate of the fourthstorage transistor 140.

FIG. 1C is a diagram of a dual-port memory cell, as may be used inembodiment(s) of the innovations herein. This example cell 102 may storea bit on four transistors 171, 172, 173, 174 that form two inverters.Access transistors 175, 176, 177, 178 may control access to the storagetransistors during a read or write operation. Wordline A 183 andwordline B 184 may control the access transistors and thereby connectthe cell 102 to the bit lines, bit line A 181A and bit line B 181B, andto the complement bit lines, complement bit line A 182A and complementbit line B 182B. The bit lines, in turn, transfer data to and from thecell 102 during read and write operations.

FIG. 2 is a diagram of a static random access memory (SRAM) 200including a sectioned bit line (SBL) 205 according to an implementationof the innovations herein. Referring to FIG. 2, one or more memory cells100 may connect to a LBL (local bit line) 210 and LBLb (complement localbit line) 220. In the example of FIG. 2, the memory cells are shown as6T memory cells 100, though other memory cells may be utilizedconsistent with aspects of the innovations herein. Further, LBL 210 mayconnect to a pass gate transistor 215, and LBLb 220 may connect to acomplement pass gate transistor 225. In some embodiments, the LBL 210may connect to the drain of the pass gate transistor 215, and the LBLb220 may connect to the drain of the complement pass gate transistor 225.The pass gate transistor 215 may connect to a GBL (global bit line) 230,and the complement pass gate transistor 225 may connect to a GBLb(complement global bit line) 240. A pass gate enable signal may controlthe pass gate transistor 215 and complement pass gate transistor 225 toallow communication between the LBL 210 and GBL 230 and between the LBLb220 and GBLb 240 during read or write operations. In some embodiments,the true signal on the local bit lines 210, 220 may be passed to theglobal bit lines 230, 240, as opposed to a representation (such as aninverse) of the local bit line signal. In the illustrativeimplementation shown in FIG. 2, the pass gate enable line 260 controlsthe pair of pass gate transistors 250, coupling the local bit line tothe global line when enabled. In operation, a desired memory cell 100 isselected and the enable signal 260 is enabled, to pass the desired reador write between the selected memory cell and the global bit line 230.

Moreover, in some implementations, the SBL 205 may be pre-charged tohigh before an operation, such as when the memory cells herein areconfigured in NMOS and utilize the memory cell design andcharacteristics of NMOS (e.g., electron mobility, etc.). In suchimplementations, the local bit line herein may be pre-charged to high tokeep NMOS transistors in the active region. Accordingly, the presentsystems and methods may have one or more of the local bit lines bepre-charged to high to enable correspondingly improved operation ofactive NMOS transistors in the associated memory cell(s). Further, thepresent systems and methods may also be configured with bit linespre-charged to high to enable such improved operation through the senseamplifier, e.g., in implementations that include NMOS voltage senseamplifiers.

FIG. 3 is a diagram of an SRAM 300 including a plurality of SBLs 205according to a disclosed implementation. In this example, four SBLs 205are shown connected to a GBL 230 and GBLb 240, although other quantitiesof SBLs 205 may be provided in any given subset of SBLs. Duringoperation, there may be only one SBL 205 connected to the GBL 230 and/orGBLb 240 at any time. As described in more detail below, such sectionedbit line architecture offers greater flexibility, reduced overall bitline capacitance, bit line length reduction as well as improved memorycell stability and power reduction.

FIG. 4 is a diagram of an SRAM 400 including an SBL 405 according to adisclosed implementation. Like the SBL 205 of FIG. 2, the SBL 405 ofFIG. 4 may have a plurality of memory cells 100, an LBL 210, and an LBLb220. In this embodiment, separate read pass gate circuitry 450 and writepass gate circuitry 455 are provided. Here, for example, illustrativeread pass gate circuitry 450 may comprise two transistors 410, 420, suchas PMOS transistors, with drains coupled to their respective local bitlines. Illustrative write pass gate circuitry 455 may comprise twotransistors 415, 425, such as NMOS transistors, with drains similarlycoupled to their respective local bit lines. Further, in someimplementations, such separate read pass gate circuitry 450 and writepass gate circuitry 455 may speed up cycle time, such as when a writeoperation follows a read operation. LBL 210 may connect to a read passgate transistor 410 and write pass gate transistor 415, and LBLb 220 mayconnect to a complement read pass gate transistor 420 and complementwrite pass gate transistor 425.

The read pass gate transistor 410 may connect to a GBL 230, and thecomplement read pass gate transistor 420 may connect to a GBLb 240. Readpass gate enable signals may control the read pass gate transistor 410and the complement read pass gate transistor 420 to allow communicationbetween the LBL 210 and GBL 230 and between the LBLb 220 and GBLb 240during read operations. In this example, a single read pass gate enablesignal 460 controls the pair of read pass gate transistors 450 with thesame command. In this example, the read pass gate transistors 450 arePMOS devices, although other types of transistors may be used. Forexample, other implementations of read and write pass gateconfigurations consistent with the innovations herein includeconfigurations where NMOS transistors are utilized for both read andwrite pass gates, configurations where PMOS transistors are utilized forboth read and write pass gates, as well as configurations where bothNMOS and PMOS transistors are utilized together for both read and writepass gates.

In this embodiment, local data lines 470 may also be provided. The writepass gate transistor 415 may connect to a first local data line 471, andthe complement write pass gate transistor 425 may connect to a secondlocal data line 472. In other embodiments, the read pass gatetransistors 450 may connect to the local data lines 470, and the writepass gate transistors 455 may connect to the GBL 230 and GBLb 240. Writepass gate enable signals may control the write pass gate transistor 415and the complement write pass gate transistor 425 to allow communicationbetween the LBL 210 and first local data line 471 and between the LBLb220 and second local data line 472 during write operations. In thisexample, a single write pass gate enable signal 465 controls the pair ofwrite pass gate transistors 455 with the same command. In theillustrated implementation, the write pass gate transistors 455 may beNMOS devices, although other types of transistors may be used.

FIG. 5 is a diagram of an exemplary SRAM including an SBL withillustrative pass gate circuitry as well as illustrative equalizationand/or write recovery circuitry according to a disclosed implementation.The SRAM of FIG. 5 may include various pass gate (read and/or write)circuitry as set forth elsewhere herein. The pass gate circuitryillustrated in FIG. 5 has separate read and write enable controls, asdiscussed above, and has comparable bit line connections, as shown herein the context of a complementary pass gate cell 515 containing thevarious read/write pass gate transistors that couple the read/write passgate enable signals to the local bit line and complement local bit line,respectively. In one illustrative implementation, a complementary passgate cell 515 may comprise read pass gate circuitry including a firstPMOS transistor 502 that couples the local bit line 210 to the globalbit line 230 and a second PMOS transistor 504 that couples thecomplement local bit line 220 to the complement global bit line 240.Further, such complementary pass gate cell 515 may further comprise afirst NMOS transistor 506 that couples the local bit line 210 to thelocal data line(s) 420 and a second NMOS transistor 508 that couples thecomplement local bit line 220 to the local data line(s) 420. Moreover,all of these coupling transistors 502, 504, 506, 508 may be configuredsuch that the actual signals on the local lines are directly coupled tothe associated global bit lines or local data lines via theirsource-to-drain connections, i.e., their actual, not complementaryvalues, are provided as outputs. Referring to FIG. 5, equalizationand/or write recovery circuitry 520 is also shown, consistent withaspects of the innovations herein. This circuitry 520 may be configuredas bit line equalization circuitry, as write recovery circuitry, or asboth. In the illustrated implementation, such circuitry 520 includes afirst transistor 522 with drain coupled to the local bit line, a secondtransistor 524 with drain coupled to the local complement bit line, anda third transistor 526 with source coupled to the local bit line anddrain coupled to the local complement bit line, wherein gates of thefirst, the second and the third transistors are coupled together to anequalization enable signal. Further, in some implementations, the firsttransistor 522, the second transistor 524, and the third transistor 526may be PMOS transistors.

Here, as a function of such configurations, local bit line equalizationmay be achieved by way of equalizing the global bit line as long as theread pass gate of the SBL is on. Further, an advantage of such systemsand methods is that chip surface area is reduced by removing the needfor local equalization components. But, in someoperations/implementations, other issues may exist, such as longer cycletime because the equalization cannot begin until after the sensing ofthe bit line is completed. In implementations herein, however, byincluding the bit line equalization into sectioned bit line, the bitline equalization may start earlier by shutting off read pass gate(s)without affecting unfinished sensing on the global bit line. Further,since the sectioned bit line is short, the associated local equalizationresponse is correspondingly small. Accordingly, the area penalty is alsosmall for such implementations, though the advantages of reducing cycletime/operation are more than enough to justify the extra area.

FIG. 6 is a diagram of an SRAM 600 including a plurality of SBLs 205configured in a row with a sense amplifier according to a disclosedimplementation. In the illustrated implementation, the SRAM 600 has aconfiguration similar to the SRAM 300 of FIG. 3, but with a senseamplifier 610 shown. The sense amplifier 610 may detect and amplifysignals on the GBL 230 and GBLb 240, for passing along to the circuitryaccessing the SRAM. The plurality of SBLs 205 may be arranged in asingle row in the bit line direction to form the GBL 230 and GBLb 240.

Bit line length in such SRAM circuits (i.e., overall or effective bitline length) may be given, approximately, as the sum of the SBL lengthand the GBL length. In order to reduce overall bit line length,implementations herein include SBLs arranged into matrices of multiplecolumns and rows that optimize the global bit line length. FIG. 7 is adiagram of an SRAM 700 including a plurality of SBLs 205 according toone such illustrative implementation of the innovations herein.Referring to FIG. 7, SBLs 205 may be arranged into a matrix of multiplecolumns and rows, which may reduce the overall bit line length otherwisepresent. In the example SRAM 700 of FIG. 7, the SRAM section shown isarranged into four columns of SBLs, although different arrangements arepossible. Each of the columns may be regarded as a section 710. Thus, asused herein, connections between sections 710 and the global bit lines230, 240 may be provided via local section lines 720.

FIG. 7 illustrates that global bit line may be shortened by implementingsuch plural SBLs arranged in multiple rows and columns to reduce globalbit line length at the same time maintaining the memory array density.Further, such configurations entail additional column decoding requiredto achieve SBL matrix. Since there are many SBLs that are directlyconnected to the GBL, so there should be only one SBL that can beconnected to the GBL at any time.

Further, consistent such configurations and the considerations andinnovations set forth herein, the present implementations may comprisemultiple bit lines sharing a sense amplifier with multiple SRAM cellsselected. Further, such selected SRAM cells may be connected to bothtrue and complement bit lines. In some such embodiments, the pass gateson true and complement local bit lines may be configured for selectionat the same time. In other implementations, a word line may selectmultiple memory cells on multiple bit line pairs. Moreover, bit lines invarious implementations herein may be charged to full Vcc of the SRAM.

Moreover, from a fabrication standpoint, SRAMs consistent with theinnovations herein may be configured such that the global bit linesand/or control signals are formed in layers above or below the memorycells, i.e., on higher/lower level(s). See, for example, FIGS. 15A-15D.Such configurations provide better tracking in relation to theassociated control signal(s), especially as against sense amplifierenable signal(s) and the SBL selection signals for SRAMs.

FIG. 8 is a diagram of local connections of a plurality of SBLs 205 inan SRAM 800 according to an embodiment of the invention. FIG. 8 showsthe local connections of the embodiment of FIG. 7 in greater detail. TheSRAM may comprise a plurality of SBLs 205 which may be linked to LBLs210 and LBLbs 220. In the illustrative implementation shown here, eightpairs of LBLs 210 and LBLbs 220 are provided. Each LBL 210 may have atleast one associated read pass gate 410 and write pass gate 415, andeach LBLb 220 may have at least one associated read pass gate 420 andwrite pass gate 425. As described above, the read pass gates 410, 420may be controlled by read pass gate enable signals 460, and the writepass gates 415, 425 may be controlled by write pass gate enable signals465.

As shown in FIG. 8, local section lines 720 may include LSL 722, LSLb724, LDL 820, and LDLb 830. In this embodiment, LSL 722 and LSLb 724 maybe used for write operations and may not be connected to the GBL 230 andGBLb 240. If they are not connected to the GBL 230 and GBLb 240, the LSL722 and LSLb 724 do not directly contribute any loading to the GBL 230and GBLb 240. Further, in some certain implementations, the LDL 820 andLDLb 830 may even be used for read operations. The pass gates 410, 415,420, 425 associated with the SBLs 205 may be drawn in the bit line pitchof the SRAM 700 so multiple SBLs 205 may be arranged side by side.

Referring to FIG. 8, the local section lines 720 may be shorter and lesscapacitive than that of SBL since the length of lsl and lslb is onlythat of few memory cells. In one illustrative implementation, forexample, systems may be configured with 8 SBLs connected to the lsl andlslb (see, e.g., FIG. 8), wherein the length of lsl or lslb is onlyabout 4 bit line pitch width, which is very insignificant as compared tothe length of local sectioned bit line or global bit line length.

With regard to implementations such as those shown in FIGS. 7 and 8,some simplified illustrations of sectioned bit line of FIG. 7 are shownin FIGS. 5 and 10, as explained in more detail above and below.

FIGS. 9A-9C show an exemplary comparison of a conventional SRAM bit linescheme (FIG. 9A) with two SBL configurations (FIGS. 9B-9C). Aconventional SRAM 900 with a plurality of memory cells 100 and bit lines900, 910 is shown in FIG. 9A. For example, the SRAM 900 may have Nmemory cells 100. FIG. 9B is a diagram of an SRAM 950 including aplurality of SBLs 205 according to an embodiment of the invention. TheSRAM 950 may also have N memory cells 100, but the memory cells 100 maybe arranged within four SBLs 205, in this example. The memory cells 100may be divided among other numbers of SBLs 205 in other embodiments.Global bit line length for the SRAM 900 without local bit lines and theSRAM 950 comprising local bit lines may be similar. However, the totaljunction capacitance of the SRAM 950 comprising local bit lines and fourSBLs 205 may be approximately one quarter of the junction capacitance ofthe SRAM 900 without local bit lines. The global bit line length andcapacitance may be further reduced by arranging the four SBLs 205 intotwo rows and two columns, as shown by the SRAM 980 of FIG. 9C. Theglobal bit line length of SRAM 980 may be approximately half that ofSRAM 950, and the global bit line length of SRAM 980 may beapproximately the same as that of an SBL 205. The sectioned bit linearchitecture may offer many ways to arrange components to affect speedand power consumption.

FIG. 10 is a diagram of an illustrative SRAM including an SBL withillustrative pass gate circuitry as well as illustrative equalizationand/or write recovery circuitry according to a disclosed implementation.Referring to FIG. 10, exemplary SRAM circuitry is disclosed, which mayinclude pass gate circuitry having separate read and write enablecontrols, as discussed above, and may have comparable bit lineconnections. Further, various pass gate (read and/or write) or othercircuitry may be included, as set forth elsewhere herein. For example,the SRAM circuitry may include equalization and/or write recoverycircuitry 520, such as in FIG. 5, consistent with aspects of theinnovations herein. This circuitry 520 may be configured as bit lineequalization circuitry, as write recovery circuitry, or as both. In theillustrated implementation, such circuitry 520 may includes a firsttransistor with drain coupled to the local bit line, a second transistorwith drain coupled to the local complement bit line, and a thirdtransistor with source coupled to the local bit line and drain coupledto the local complement bit line, wherein gates of the first, the secondand the third transistors are coupled together to an equalization enablesignal. Further, in some implementations, these transistors may be PMOStransistors. Moreover, with regard to the pass gate circuitry, FIG. 10illustrates another exemplary implementation of a complementary passgate cell 1015 containing the various read/write pass gate transistorsthat couple the read/write pass gate enable signals to the local bitline and complement local bit line, respectively.

In one illustrative implementation, such complementary pass gate cell1015 may comprise read pass gate circuitry including transistor pairsbetween the local bit lines and the global bit lines, such pairsincluding first transistors 1004, 1008 with gates connected to the localbit line and complement local bit line, respectively, and sourcescoupled to drains of second transistors 1002, 1006 that have gatescoupled to the read pass enable signal and sources connected to thecomplement global bit line 240 and global bit line 230, respectively.Further, such complementary pass gate cell 1015 may further comprise afirst NMOS transistor 1010 that couples the local bit line 210 to thelocal data line(s) 420 and a second NMOS transistor 1012 that couplesthe complement local bit line 220 to the local data line(s) 420.Moreover, these coupling transistors or these combinations of couplingtransistors may be configured such that the actual signals on the locallines are directly coupled to the associated global bit lines or localdata lines via their source-to-drain connections, i.e., their actual,not complementary, values are provided as outputs.

Further, e.g. in implementations such as that of FIG. 8, multiple levelcolumn decoding may be utilized to provide proper connection to the GBL,which may be configured in the same direction as local bit lines.Additionally, as shown by way of one illustration in FIG. 18, the localsense amplifier enable signal and/or the local data driver enablesignal, with regard to the memory cells layout, may also be configuredin the same direction as local bit line. Indeed, in someimplementations, the local sense amplifier enable and local data driverenable are part of Y (column) decoding of the global bit line. Moreover,such SRAMs and associated method herein may be implemented such that thelocal select (LS) is a function of X decoding. Further, in someimplementations, local select (LS) and local pass gate enable signals(Rpb and Wp) may be configured in the word line direction.

FIGS. 11 and 12 are diagrams of illustrative SRAMs including SBLs, 8Tmemory cells and associated read and write pass gates according todisclosed implementations. As with the previous implementations, theSBLs of FIGS. 11 and 12 may have a plurality of 8T memory cells 101,local data lines 1170, as well as local and global bit lines. Theimplementations of FIGS. 11 and 12 include a write local bit line 1110,a read local bit line 1112 and a complement write local bit line 1120.In the embodiment of FIG. 11, separate read pass gate circuitry 1132Aand write pass gate circuitry 1131A are provided. Here, for example,illustrative write pass gate circuitry 1131A may comprise twotransistors 1115A, 1125A, such as NMOS transistors, with drains coupledto their respective local bit lines, write local bit line 1110 andcomplement write local bit line 1120. Illustrative read pass gatecircuitry 1132A may comprise a transistor 1130A, such as PMOStransistor, with drain coupled to its respective read local bit line1112. Again, in some implementations, such separate read pass gatecircuitry and write pass gate circuitry may speed up cycle time, such aswhen a write operation follows a read operation.

Referring to FIG. 11, the read pass gate transistor 1130A may connect toa GBL 1105. Further, a read pass gate enable signal 1160 may control theread pass gate transistor(s) to allow communication between the localand global bit lines during read operations. In this example, the readpass gate transistor 1130A may be a PMOS device, although other types oftransistors may be used.

In this embodiment, local data lines 1170 may also be provided. A firstwrite pass gate transistor 1115A may connect to a first local data line,and the complement write pass gate transistor 1125A may connect to asecond local data line. In this example, a single write pass gate enablesignal 1140 may control the pair of write pass gate transistors with thesame command. In the illustrated implementation, the write pass gatetransistors 1115A, 1125A may be NMOS devices, although other types oftransistors may be used.

In the embodiment of FIG. 12, an integrated and/or “complementary” passgate circuit 1134 may be provided. Here, for example, the read/writetransistors and control functionality set forth above may be integratedinto a structurally, functionally and/or electrically unitary module orcomponent. In particular, control and signals provided to suchintegrated circuitry may be configured as complementary circuitry toprovide greater efficiency, decreased size, reduction in cost, or thelike.

Overall, the decision of which such pass gate structures to use may be adetermination performed as a function of structural and/or layoutconsiderations, such as issues of separation of the read bit line fromthe write bit line, need for better memory cell stabilization, higherspeed, and/or lower power, among other desires.

FIGS. 13 and 14 are diagrams of illustrative SRAMs including SBLs,dual-port memory cells and associated read and write pass gatesaccording to disclosed implementations. Referring to FIG. 13, a firstimplementation involving dual-port memory cells 102 is shown. Here, eachsection bit line may include local bit line A and its complement 1302,1304 as well as local bit line B and its complement 1306, 1308 coupledto the memory cells 102. Further, write pass gate circuitry 1320 may beconnected between the local bit lines and the local data lines 1318 andread pass gate circuitry 1330 may be connected between the local bitlines and the global bit lines (global bit line A and its complement1310, 1312 and global bit line B and its complement 1314, 1316).

Write pass gate circuitry 1320 may include transistors/componentscoupled to a first write pass gate signal 1329 including a firstcoupling transistor 1322 connected between local bit line A 1302 and thelocal data line 1318 and a second coupling transistor 1324 connectedbetween the complement local bit line A 1304 and the local data line1318. Write pass gate circuitry may also include transistors/componentscoupled to a second write pass gate signal 1329 including a firstcoupling transistor 1326 connected between local bit line B 1306 and thelocal data line 1318 and a second coupling transistor 1328 connectedbetween the complement local bit line B 1308 and the local data line1318. In some embodiments, such coupling transistors 1322, 1324, 1326,1328 may be NMOS transistors. Further, in certain implementations, suchcoupling transistors may be connected to the local bit lines via theirdrains, to enable passing of true (not inverse) local bit line values tothe global bit lines.

Read pass gate circuitry 1330 may include transistors/components coupledto a first read pass gate signal 1339 including a first couplingtransistor 1332 connected between local bit line A 1302 and global bitline B 1314 and a second coupling transistor 1334 connected between thecomplement local bit line A 1304 and the complement global bit line B1316. Read pass gate circuitry 1330 may also includetransistors/components coupled to a second read pass gate signal 1339including a first coupling transistor 1336 connected between local bitline B 1306 and global bit line A 1310 and a second coupling transistor1338 connected between the complement local bit line B 1308 and globalbit line A 1312. In some embodiments, such coupling transistors 1332,1334, 1336, 1338 may be PMOS transistors. Further, in certainimplementations, such coupling transistors may be connected to the localbit lines via their drains, to enable passing of true (not inverse)local bit line values to the global bit lines.

Referring to FIG. 14, a second implementation involving dual-port memorycells 102 is shown. Here, each section bit line may include local bitline A and its complement 1402, 1404 as well as local bit line B and itscomplement 1406, 1408 coupled to the memory cells 102. Further, acomplementary pass gate cell 1420 including write pass gate circuitryand read pass gate circuitry may be connected between the local bitlines and the global bit lines 1410, 1412, 1414, 1416 or the local datalines 1418.

Within the complementary pass gate cell 1420, write pass gate circuitrymay include transistors/components coupled to a first of the write passgate signals 1429 including a first coupling transistor 1422 connectedbetween local bit line A 1402 and the local data line 1418 and a secondcoupling transistor 1424 connected between the complement local bit lineA 1404 and the local data line 1418. Such write pass gate circuitry mayalso include transistors/components coupled to a second of the writepass gate signals 1429 including a first coupling transistor 1426connected between local bit line B 1406 and the local data line 1418 anda second coupling transistor 1428 connected between the complement localbit line B 1408 and the local data line 1418. In some embodiments, suchcoupling transistors 1422, 1424, 1426, 1428 may be NMOS transistors.Further, in certain implementations, such coupling transistors may beconnected to the local bit lines via their drains, to enable passing oftrue (not inverse) local bit line values to the global bit lines.

Also within the complementary pass gate cell 1420, read pass gatecircuitry may include transistors/components coupled to a first of theread pass gate signals 1439 including a first coupling transistor 1430connected between local bit line A 1402 and global bit line B 1414 and asecond coupling transistor 1432 connected between the complement localbit line A 1404 and the complement global bit line B 1416. Such readpass gate circuitry may also include transistors/components coupled to asecond of the read pass gate signals 1439 including a first couplingtransistor 1434 connected between local bit line B 1406 and global bitline A 1410 and a second coupling transistor 1436 connected between thecomplement local bit line B 1408 and global bit line A 1412. In someembodiments, such coupling transistors 1430, 1432, 1434, 1436 may bePMOS transistors. Further, in certain implementations, such couplingtransistors may be connected to the local bit lines via their drains, toenable passing of true (not inverse) local bit line values to the globalbit lines.

Additionally, from a fabrication/structural standpoint, SRAMs consistentwith the innovations herein may be configured such that the global bitlines and/or control signal lines are formed in layers above or belowthe memory cells, i.e., on higher/lower level(s). Here, for example,FIGS. 15A-15D illustrate various illustrative implementations whereinthe local bit lines and/or the global bit lines or control signal linesare formed above or below the memory cell array. As shown in theillustrated embodiments, local bit lines and power buses may be formedin metal 2 1506, word lines and power buses may be formed in metal 31504, and global bit lines, control signal lines and power buses may beformed in metal 4 1502. Moreover, according to some such configurations,in addition to savings such as in chip area and/or cost, improvedtracking may be provided in relation to the associated control signal(s)with such structures, especially as against sense amplifier enablesignal(s) and the SBL selection signals for SRAMs.

Additionally, according to simulations analysis in the relevanttechnology, a 1K block (1024) of memory cells arranged into four SBLs ina 2×2 matrix consistent with the innovations herein has approximately50% less capacitance in comparison to a conventional 1K memory cell bitline. In some implementations, the bit line parasitic capacitancereduction from aforementioned analysis is about 45% that of conventionalbit line, and the junction capacitance reduction from aforementionedanalysis is about 60% less that of conventional bit line. As such,implementations herein may achieve a total combined capacitancereduction of about 50%. Such analyses also show that a 2K block (2048)of memory cells utilizing the illustrative 2×2 SBL matrices consistentwith the innovations herein may have a bit line capacitance that isapproximately 50% less than that of a conventional 2K memory cells bitline. Therefore, as a results of present innovations utilizing thesectioned bit line architecture(s) set forth above, systems and methodsherein may approximately double the memory array density whilemaintaining the same speed and operation.

Moreover, in another set of embodiments, SRAM systems and methods may beprovided that utilize sectioned bit lines in a hierarchical columnmemory array. Consistent with such embodiments, systems and methodsherein may reduce bit line capacitance and/or improve speed. Here, forexample, sectioned bit lines may include a plurality of memory cellsthat connect onto true and complement local bit lines, where each of thelocal bit lines couples to the global bit lines. In someimplementations, a local sense amplifier may be added between asectioned bit line and a global bit line, which may further reduce theoverall bit line length because the active sectioned bit line is furtherisolated from the global bit line. A local data driver may be addedalong with a local sense amplifier to facilitate the writing of new datato memory cells in the SBL. The SBLs with the local sense amplifier andlocal data drivers may form a mini array on the global bit lines.Structurally, then, an exemplary hierarchical column memory array mayinclude such SBLs and GBLs.

FIG. 16 illustrates the global bit lines with a local connection of SBLsarranged in multiple rows and columns, according to an exemplaryimplementation. As discussed previously in connection with FIGS. 3 and6, plural SBLs can be connected on to the global bit line and globalcomplement bit line where the SBLs are arranged in a single row. In thisarrangement, the global bit lines have to be implemented on the top ofthe local bit lines of the SBL and the width of the global bit line isalso limited to the local bit line width of the SBL. FIG. 16 disclosesan implementation that improves on the RC time constant of the globalbit line by arranging the SBL into multiple rows and columns such thatthe global bit line width is not limited to a local bit line width. InFIG. 16, two rows and four columns of SBLs 205 are connected onto theglobal bit lines 230, 240 via the local connection 1600. In such aconfiguration, the RC time constant of the global bit line can beoptimized with a wider width such that the global bit line is muchshorter. Furthermore, by arranging the SBLs to include a plurality ofrows and columns is that more SBLs can be accommodated on the sameglobal bit line length of the single column.

In some implementations, for example, eight SBLs in four rows may beconnected locally before connection to the corresponding GBLs. Oneimplementation of the detailed local connection of the eight SBLs isillustrated in FIG. 8. Within the local connection, eight pairs of readpass gates are provided coupled to local data lines Ldl and Ldlb. Whenone of the eight pairs of read pass gates is enabled, the selected localbit lines are connected to the Ldl and Ldlb. Only one pair of pass gatesis enabled at any one time, no matter whether it is read or write, andthus only one SBL is coupled onto the GBL at any one time. The selectionof SBL and the pass gates may be achieved through column decoding. Thelocal connection is not limited to eight SBLs and can be expanded tosixteen SBLs, thirty-two SBLs, etc. However, a larger number of SBLsrequires a larger space to accommodate the larger number of columndecoding lines and also increases the capacitance of the localconnection. As such, for certain implementations, the total number ofSBLs in the local connection 1600 may be limited to eight or sixteen.

Next, FIG. 17 illustrates a configuration including a plurality of localconnections on the global bit lines, according to one exemplaryimplementation. Providing multiple local connections is difficult in alarge array because the selection and de-selection of SBLs in a localconnection is achieved solely by the column decoding which means thecolumn decoding of each of the local connections must be unique. Thedifficulty increases as the number of local connections increases.Therefore, there is a need to simplify the decoding of the localconnections and improve upon the RC time constant. Aspects of thepresent innovations may solve such issues by including a local senseamplifier and local data drivers are implemented for the localconnections as a means to add control.

FIGS. 18, 19A and 19B disclose implementations of the local connection1600 with a local sense amplifier and data driver 1800, according toexemplary implementations. The local connection 1600 in FIG. 18 iscontrolled by the decoded local select LS[0] and LS[1]. Hence, bothlocal connections illustrated can share the same column decoding withoutbus contention occurring on the GBLs. Further, with the sense amplifierenable SAE and the write enable WE, the read and write operations may becontrolled individually in each local connection 1600.

FIGS. 19A and 19B illustrates one detailed arrangement of a local senseamplifier 1920 and local data driver 1940 (1940A or 1940B), according toexemplary implementations. The increase in area due to the local senseamplifier 1920 and local data driver 1940 in a local connection 1600 maybe minimized by the configuration shown in FIG. 19. The decoded localsignal LS[0] enables either the sense amplifier (read operation) or thedata drivers (write operation). The read and write enable signals SAEand WE in FIG. 18 are able to reach the local sense amplifier 1920 anddata driver 1940 in each local connection 1800 via the top of the SBLsdue to the multiple column format of the SBLs. Accordingly, from thepoint of view of the GBL, the read and write enables become theconventional decoding of the GBL.

Furthermore, in FIGS. 19A and 19B, the read and write operations of theSBL with local sense amplifier 1920 and data drivers 1940 operate thesame as that of a regular memory array. Before the read operationbegins, the local bit lines in the SBLs and Lsl and Lslb are prechargedto Vdd. Memory cells are turned on by an active word line WL0, forexample. At the same time, the read pass gate enable such as Rpb[0] ofRpbp[0:7] enables one of the eight pairs of read pass gates. Thus, theselected SBL with the selected memory cell is coupled onto the Lsl andthe Lslb. The prerequisite of activation of the local sense amplifier1920 is the activation of the signal LS[0]. When both the LS[0] and SAEare active, logic high in this example, the local voltage senseamplifier is enabled. Although a voltage sense amplifier is used in thisexample, other types of sense amplifiers may be implemented based ondesign requirements. With proper timing, the sense amplifier enables theSAE signal to turn on the local voltage sense amplifier to amplify thevoltage changes presented on the Lsl and Lslb by the memory cell. In themeantime, the amplified signal on the Lsl and Lslb is transferred to theglobal bit lines.

Similarly, for the write operation, the local bit lines at the start inthe SBLs, Ldl and Ldlb are precharged to Vdd. Memory cells are turned onby an active word line, for example WL0. At the same time, the writepass gate enable such as Rpb[0] of Rpb[0:7] enables one of the eightpairs of write pass gates. Thus, the selected SBL with the selectedmemory cell are coupled to the Ldl and Ldlb. All other pass gates shouldbe inactive during this time to ensure proper writing operation. Whenboth LS[0] and WE are active, logic high in this example, the local datadrivers convert the data on the global data line GDL into differentialdata on the Ldl and Ldlb that are needed for write operation. Writing onthe memory cell is thereby initiated when WE is active. As shown in theillustrative implementation of FIGS. 19A and 19B, the global bit linemay be used as global data line, thus the need for the global data lineis eliminated.

The local section bit line block LSBL 2000 is illustrated in FIG. 20.The LSBL 2000 includes a plurality of SBLs, a local sense amplifier1920, a data driver 1940 and corresponding enable signals WE and SAE.FIG. 21 illustrates an array of LSBLs with a local column select, localselect, and read and write enables. A global sense amplifier 2140 may beprovided at the end of the GBL to receive the amplified signals from thelocal sense amplifiers 1920 in the LSBLs. The local sense amplifier 1920may serve as the pre-amplifier to the GBL sense amplifier 2140. In aconventional memory array, there would be provided pass gates betweenthe GBL and the global bit line sense amplifier 2140. However, with theconfiguration of the present invention, pass gates are unnecessary. TheSAE2 and WE2 are respective read and write enables for the global senseamplifier 2140 and global data line driver 2120.

Next, FIG. 22 is a diagram of a hierarchical column array of SBLs withlocal sense amplifiers and data drivers. In particular, the local selectLS, write enable WE and sense enable signal SAE form an XY grid toprovide LSBL array decoding. The word line decoding generates decodedword lines to turn on the memory cells in the SBL. The local columndecoding generates the decoded read and write pass gate enables as wellas the decoded local select signals in the word line direction for theLSBL array. The GBL column decoding generates the GBL read and writeenables WE1 and SAE1 as well as the GBL sense amplifier enable andglobal data driver enable SAE2 and WE2, respectively, in the columndirection. The GBL sense amplifier 2140 will receive the amplifiedsignal from the local sense amplifier 1920 on the GBL to complete theread operation and then transfer the read data to the periphery of thememory array. The hierarchical column scheme organizes the LSBL into alarge hierarchical array where the LSBLs are linked together where theLSBL is formed by a plurality of SBLs, local sense amplifiers and localdata drivers.

Systems and methods involving an SBL, local sense amplifier and/or alocal data driver provide many advantages. For example, the local senseamplifier amplifies signals from the SBL and isolates the SBL from theglobal bit lines to improve not only the RC time constant of the SBL,but also that of the GBL. The local data drivers may convert the globaldata line GDL into local data lines Ldl and Ldlb, thereby improving datadistribution over a large array. Power consumption may also be reducedas unnecessary charging and discharging of local data lines iseliminated. Thus, memory cell stability is improved and, further, thelocal bit line of the SBL may be less capacitive. As such, thehierarchical column array systems and methods described above mayprovide flexibility, reduce bit line capacitance, bit line length andpower usage, and/or result in improved memory cell stability.

While various embodiments have been described above, it should beunderstood that they have been presented by way of example and notlimitation. It will be apparent to persons skilled in the relevantart(s) that various changes in form and detail can be made thereinwithout departing from the spirit and scope. For example, other memorycells beside 6T memory cells may be used in sectioned bit line, such as4T, dual ports, and 1T memory cells. Also, the sectioned bit linearchitecture described herein may be adapted into different memory arrayconfigurations and memory compilers. In fact, after reading the abovedescription, it will be apparent to one skilled in the relevant art(s)how to implement alternative embodiments. Thus, the present embodimentsshould not be limited by any of the above-described embodiments.

In addition to the above SRAMs and SRAM architecture, the presentinventions also include, inter alia, methods of SRAM operation, methodsof fabricating SRAM devices consistent with the features and/orfunctionality herein, products (such as SRAMs or products embodyingSRAMs), and products produced via such processes. By way of example andnot limitation, methods of SRAM fabrication herein may include knownSRAM manufacturing processes such as in CMOS technologies involvingaspects such as p-mos and n-mos transistor formation, multiplemetallization layers and/or local interconnects, among others. A varietyof exemplary/staple processes here, for example, being set forth in thebackgrounds/disclosures of U.S. Pat. Nos. 4,794,561, 5,624,863,5,994,178, 6,001,674, 6,117,754, 6,127,706, 6,417,549, 6,894,356, and7,910,427 as well as U.S. patent application publication No.US2007/0287239A1, which are incorporated herein by reference.

Further, it should be understood that any figures which highlightfunctionality and advantages are presented for example purposes only.The disclosed methodologies and systems are each sufficiently flexibleand configurable such that they may be utilized in ways other than thoseshown.

Aspects of the method and system described herein, such as the logic,may be implemented as instructions/signals associated with orfunctionality related to a variety of circuitry, including programmablelogic devices (“PLDs”), such as field programmable gate arrays(“FPGAs”), programmable array logic (“PAL”) devices, electricallyprogrammable logic and memory devices and standard cell-based devices,as well as application specific integrated circuits. Some otherpossibilities for implementing aspects include: memory devices,microcontrollers with memory (such as EEPROM), embedded microprocessors,firmware, software, etc. Furthermore, aspects may be embodied inmicroprocessors having software-based circuit emulation, discrete logic(sequential and combinatorial), custom devices, fuzzy (neural) logic,quantum devices, and hybrids of any of the above device types. Theunderlying device technologies may be provided in a variety of componenttypes, e.g., metal-oxide semiconductor field-effect transistor(“MOSFET”) technologies like complementary metal-oxide semiconductor(“CMOS”), bipolar technologies like emitter-coupled logic (“ECL”),polymer technologies (e.g., silicon-conjugated polymer andmetal-conjugated polymer-metal structures), mixed analog and digital,and so on.

Unless the context clearly requires otherwise, throughout thedescription and the claims, the words “comprise,” “comprising,” and thelike are to be construed in an inclusive sense as opposed to anexclusive or exhaustive sense; that is to say, in a sense of “including,but not limited to.” Words using the singular or plural number alsoinclude the plural or singular number respectively. Additionally, thewords “herein,” “hereunder,” “above,” “below,” and words of similarimport refer to this application as a whole and not to any particularportions of this application. When the word “or” is used in reference toa list of two or more items, that word covers all of the followinginterpretations of the word: any of the items in the list, all of theitems in the list and any combination of the items in the list.

It should also be noted that the terms “a”, “an”, “the”, “said”, etc.signify “at least one” or “the at least one” in the disclosure andclaims.

Although certain presently preferred implementations of the inventionhave been specifically described herein, it will be apparent to thoseskilled in the art to which the invention pertains that variations andmodifications of the various implementations shown and described hereinmay be made without departing from the spirit and scope of theinvention. Accordingly, it is intended that the invention be limitedonly to the extent required by the appended claims and the applicablerules of law.

1. An SRAM memory device comprising: a local section bit line including:a plurality of sectioned bit lines (SBLs), each comprising: a local bitline; one or more memory cells connected to the local bit line; a localcomplement bit line connected to the memory cell; & a pass gate coupledto the local bit line; a local sense amplifier; a local shared datadriver; a global bit line; wherein the local sense amplifier isconfigured to amplify a signal on a local sense line and provide anoutput to the global bit line.
 2. The device of claim 1 wherein the passgates are configured to connect and/or isolate the sectioned bit lineand local sense line.
 3. A local section bit line (LSBL) of an SRAMincluding: a plurality of sectioned bit lines (SBLs), each comprising: alocal bit line; one or more memory cells connected to the local bitline; a local complement bit line connected to the memory cell; and apass gate coupled to the local bit line; a local shared sense amplifier;a local shared data driver; a global bit line; wherein the local senseamplifier is configured to amplify a signal on a local sense line andprovide an output to the global bit line.
 4. The device of claim 3wherein the pass gates are configured to connect and isolate thesectioned bit line and local sense line.
 5. The device of claim 1 or theinvention of any claim herein wherein the one or more memory cellscomprise: 2 or more LSBLs arranged in direction along the bit line (Ydirection).
 6. The device of claim 1, claim 5 or the invention of anyclaim herein wherein the one or more memory cells comprise: at least oneLSBL arranged in a direction of a word line (X direction).
 7. The deviceof claim 1 or the invention of any claim herein further comprising atleast one local sense amplifier and/or at least one local data driver.8. The device of claim 1 or the invention of any claim herein wherein atleast two or more local sense amplifiers and/or at least two or morelocal data drivers are configured for selection by X and Y addresses. 9.The device of claim 1 or the invention of any claim herein, furthercomprising a global data line.
 10. The device of claim 1 or theinvention of any claim herein, wherein the global bit line is configuredto be used as a global data line.
 11. The device of claim 1 or theinvention of any claim herein further comprising multiple level columndecoding circuit on the global bit line.
 12. The device of claim 11wherein the global bit line is arranged in a same direction as the localbit line(s).
 13. The device of claim 1 or the invention of any claimherein further comprising at least one multiple level sense amplifierscoupled with one or more of the global bit lines and/or the sectionedbit lines.
 14. The device of claim 1 or the invention of any claimherein further comprising at least one multiple level data drivercoupled with one or more of the global bit lines and/or the sectionedbit lines.
 15. The device of claim 1 or the invention of any claimherein further comprising a single global bit line sense amplifier forone or more of the local section bit lines (LSBLs).
 16. The device ofclaim 1 or the invention of any claim herein further comprising a singleglobal data driver for one or more of the local sectioned bit lines(LSBLs).
 17. The device of claim 1 or the invention of any claim hereinwherein the global bit lines, local sense amplifier enable lines, andlocal data driver enable lines (signals) on memory cells layout arearranged in a same direction as the local bit lines.
 18. The device ofclaim 1 or the invention of any claim herein further comprising a localsense amplifier enable line and/or a local data driver enable lineconfigured as part of Y (column) decoding of the global bit line. 19.The device of claim 1 or the invention of any claim herein furthercomprising local select (LS) lines configured and/or connected as afunction of X decoding.
 20. The device of claim 1 or the invention ofany claim herein further comprising one or more local select (LS) linesand/or one or more local pass gate enable lines (Rpb and Wp) configuredin a word line direction.
 21. An SRAM memory device comprising: a localsection bit line including: a plurality of sectioned bit lines (SBLs),each comprising: a local bit line; one or more memory cells connected tothe local bit line; a local complement bit line connected to the memorycell; & a pass gate coupled to the local bit line; a local shared senseamplifier; a local shared data driver; a global bit line; and a dummyglobal bit line that is arranged along or in a comparable path of theglobal bit line; wherein the local sense amplifier is configured toamplify a signal on a local sense line and provide an output to theglobal bit line.
 22. The device of claim 21 wherein the pass gates areconfigured to connect and/or isolate the sectioned bit line and localsense line.
 23. The device of claim 21 or the invention of any claimherein further configured to utilize the dummy global bit line toemulate delay on the global bit line for better timing tracking.
 24. Theinvention of claim 23 wherein the timing tracking that is improvedincludes timing tracking between at least one of the local senseamplifiers and at least one of the global sense amplifiers.
 25. Theinvention of claim 21 further comprising circuitry configured to: accessa plurality of sectioned bit lines, the sectioned bit lines beingsections of a global bit line, each sectioned bit line comprising a bitline, one or more memory cells connected to the bit line, a complementbit line connected to the memory cell, and a pass gate coupled to thebit line, wherein a dummy global bit line is arranged along or in acomparable path of the global bit line; pass data/signals to or frommemory cells within the sectioned bit line via the pass gates, whereinthe pass gates are configured to connect and isolate the sectioned bitlines and the global bit line; determine an estimated delay on theglobal bit line via measurement of emulated delay information on thedummy global bit line; and utilize the estimated delay and/or theemulated delay information to improve timing tracking.
 26. A method ofSRAM operation comprising: accessing a plurality of sectioned bit lines,the sectioned bit lines being sections of a global bit line, eachsectioned bit line comprising a bit line, one or more memory cellsconnected to the bit line, a complement bit line connected to the memorycell, and a pass gate coupled to the bit line, wherein a dummy globalbit line is arranged along or in a comparable path of the global bitline; passing data/signals to or from memory cells within the sectionedbit line via the pass gates, wherein the pass gates are configured toconnect and isolate the sectioned bit lines and the global bit line;determining an estimated delay on the global bit line via measurement ofemulated delay information on the dummy global bit line; and utilizingthe estimated delay and/or the emulated delay information to improvetiming tracking.
 27. The method of claim 26 wherein the timing trackingthat is improved includes timing tracking between at least one of thelocal sense amplifiers and at least one of the global sense amplifiers.28. The invention of any claim herein wherein at least one of the globalbit line are formed on one or more layers above the memory cell and/oron one or more layers below the memory cell.
 29. The invention of anyclaim herein, wherein at least one of the control signal lines areformed on one or more layers above the memory cell and/or on one or morelayers below the memory cell.
 30. A method of SRAM operation comprising:accessing a plurality of sectioned bit lines in a hierarchical memoryarray, the sectioned bit lines being sections of a global bit line, eachsectioned bit line comprising a bit line, one or more memory cellsconnected to the bit line, a complement bit line connected to the memorycell, and a pass gate coupled to the bit line; passing data/signals toor from memory cells within the sectioned bit line via the pass gates,wherein the pass gates are configured to connect and isolate thesectioned bit lines and the global bit line.
 31. A method of SRAMoperation comprising: reading/writing data to one or more of a pluralityof sectioned bit lines in a hierarchical memory array, consistent withany claim, configuration and/or aspect of the disclosure herein.
 32. Amethod of operating a local section bit line (LSBL) of an SRAMcomprising: accessing a plurality of sectioned bit lines arranged in ahierarchical memory array, the sectioned bit lines being sections of aglobal bit line, each sectioned bit line comprising a bit line, one ormore memory cells connected to the bit line, a complement bit lineconnected to the memory cell, and a pass gate coupled to the bit line;and operating the pass gates to connect and/or isolate the sectioned bitlines and the global bit lines.
 33. The method of claim 32 or theinvention of any claim herein, wherein the one or more memory cellscomprise two or more LSBLs arranged in direction along the bit line (Ydirection).
 34. The method of claim 32 or the invention of any claimherein, wherein the one or more memory cells comprise at least one LSBLarranged in a direction of a word line (X direction).
 35. The method ofclaim 32 or the invention of any claim herein, further comprising:operating at least one local sense amplifier and/or at least one localdata driver for selection by X and Y addresses.
 36. The method of claim32 or the invention of any claim herein, further comprising: decodingmultiple level columns on the global bit line.
 37. The method of claim32 or the invention of any claim herein, further comprising: performingread/write operations using the global bit line, wherein the global bitline is arranged in a same direction as the local bit line(s).
 38. Themethod of claim 32 or the invention of any claim herein, furthercomprising: amplifying a signal on the local sense line using at leastone multiple level sense amplifier, wherein the at least one multiplelevel sense amplifier is coupled to at least one global bit line and/orthe sectioned bit lines.
 39. The method of claim 32 or the invention ofany claim herein, further comprising: driving data via a multiple leveldata driver, wherein the multiple level data driver is coupled to atleast one global bit line and/or the sectioned bit lines.
 40. The methodof claim 32 or the invention of any claim herein, further comprising:amplifying a signal on the global bit line via a single global bit linesense amplifier, wherein the single global bit line sense amplifier iscoupled to one or more of the local section bit lines (LSBLs).
 41. Themethod of claim 32 or the invention of any claim herein, wherein theglobal bit lines, local sense amplifier enable lines, and/or local datadriver enable lines are arranged on memory cells in a same direction asthe local bit lines.
 42. The method of claim 32 or the invention of anyclaim herein, wherein a local sense amplifier enable line and/or a localdata driver enable line are arranged as Y direction decoding of theglobal bit line.
 43. The method of claim 32 or the invention of anyclaim herein, further comprising: selecting memory cells via localselect (LS) lines, wherein the LS lines are configured as a function ofX direction decoding.
 44. The method of claim 32 or the invention of anyclaim herein, wherein one or more local select (LS) lines and/or one ormore local pass gate enable lines are configured in a word linedirection.
 45. A method of SRAM operation comprising the steps of:accessing a plurality of sectioned bit lines arranged in a hierarchicalmemory array, the sectioned bit lines being sections of a global bitline, each sectioned bit line comprising a bit line, one or more memorycells connected to the bit line, a complement bit line connected to thememory cell, and a pass gate coupled to the bit line; passingdata/signals to or from memory cells within the sectioned bit line viathe pass gates; and operating the pass gates to connect and/or isolatethe sectioned bit lines and the global bit lines.
 46. The method ofclaim 45 or the invention of any claim herein further comprisingemulating delay of the global bit line via a dummy global bit line,wherein the dummy global bit line is arranged along or in a comparablepath of the global bit line.
 47. The method of claim 45 or the inventionof any claim herein, wherein delay is emulated for better timingtracking.
 48. The method of claim 45 or the invention of any claimherein, further comprising: determining an estimated delay on a globalbit line via measurement of emulated delay information on the dummyglobal bit line.
 49. The method of claim 45 or the invention of anyclaim herein, further comprising: performing read/write operations usingthe global bit lines, wherein at least one of the global bit lines isformed in/on one or more layers above the memory cell and/or on one ormore layers below the memory cell.
 50. The method of claim 45 or theinvention of any claim herein, further comprising: controlling operationof the SRAM via the control signal lines, wherein at least one of thecontrol signal lines is formed on one or more layers above the memorycell and/or on one or more layers below the memory cell.
 51. An SRAMmemory device comprising: a global bit line; a sectioned bit line (SBL)comprising: a local bit line; one or more memory cells connected to thelocal bit line; a local complement bit line connected to the memorycell; and a pass gate coupled to the local bit line; wherein the passgates are configured to connect and isolate the sectioned bit line andthe global bit line.
 52. The device of claim 1, claim 51 or theinvention of any claim herein, wherein a drain of the pass gate iscoupled to the local bit line.
 53. The device of claim 1, claim 51 orthe invention of any claim herein further comprising a plurality ofsectioned bit lines configured along a direction parallel to local bitlines associated with the plurality of sectioned bit lines.
 54. Thedevice of claim 1, claim 51 or the invention of any claim herein furthercomprising a plurality of sectioned bit lines configured along adirection parallel to word lines associated with the plurality ofsectioned bit lines.
 55. The device of claim 1, claim 51 or theinvention of any claim herein further comprising first modules ofsectioned bit lines (SBLs) configured along a direction parallel tolocal bit lines associated with the sectioned bit lines, and secondmodules of SBLs configured along a direction parallel to word linesassociated with the sectioned bit lines.
 56. The device of claim 1,claim 51 or the invention of any claim herein, wherein the global bitline and local bit line are oriented in a same direction.
 57. The deviceof claim 1, claim 51 or the invention of any claim herein, furthercomprising a plurality of local section lines; wherein the global bitline has an orientation that is orthogonal to an orientation of thelocal section lines.
 58. The device of claim 1, claim 51, claim 57 orthe invention of any claim herein, wherein an SBL connects to each ofthe plurality of local section lines.
 59. The device of claim 1, claim51 or the invention of any claim herein wherein the pass gate is a writepass gate defining a write path.
 60. The device of claim 59 wherein thewrite pass gate is an NMOS device.
 61. The device of claim 1, claim 51or the invention of any claim herein further comprising a read pass gatedefining a read path.
 62. The device of claim 61 wherein the read passgate is an PMOS device.
 63. The device of claim 1, claim 51 or theinvention of any claim herein, wherein the local bit line is formed on alayer above or below the SRAM memory cell.
 64. The device of claim 1,claim 51 or the invention of any claim herein, further comprisingequalization circuitry that provides bit line equalization.
 65. Thedevice of claim 64 wherein the equalization circuitry includes a firsttransistor with drain coupled to the local bit line, a second transistorwith drain coupled to the local complement bit line, and a thirdtransistor with source coupled to the local bit line and drain coupledto the local complement bit line, wherein gates of the first, the secondand the third transistors are coupled together to an equalization enablesignal.
 66. The device of claim 65 wherein the first, the second and thethird transistors are PMOS transistors.
 67. The device of claim 1, claim51 or the invention of any claim herein, further comprising writerecovery circuitry that provides write recovery of the SRAM memorydevice.
 68. The device of claim 67 wherein the write recovery circuitryincludes a first transistor with drain coupled to the local bit line, asecond transistor with drain coupled to the local complement bit line,and a third transistor with source coupled to the local bit line anddrain coupled to the local complement bit line, wherein gates of thefirst, the second and the third transistors are coupled together to awrite recovery enable signal.
 69. The device of claim 68 wherein thefirst, the second and the third transistors are PMOS transistors. 70.The device of claim 1, claim 51 or the invention of any claim hereinwherein the pass gate is a write pass gate defining a write path; andfurther comprising: a read pass gate defining a read path.
 71. Thedevice of claim 70, wherein: the write pass gate comprises an NMOSdevice; and the read pass gate comprises a PMOS device.
 72. The deviceof claim 70, wherein the write pass gate is configured to be controlledby a write operation signal.
 73. The device of claim 70, wherein theread pass gate is configured to be controlled by a read operationsignal.
 74. The device of claim 1, claim 51 or the invention of anyclaim herein wherein the local bit line and the global bit line aredisposed on a top side of the SRAM memory device.
 75. The device ofclaim 1, claim 51 or the invention of any claim herein furthercomprising bit line equalization circuitry.
 76. The device of claim 1,claim 51 or the invention of any claim herein further comprising writerecovery circuitry.
 77. The device of claim 1, claim 51 or the inventionof any claim herein wherein the memory cells comprise 6T memory cell(s).78. The device of claim 1, claim 51 or the invention of any claim hereinwherein the memory cells comprise 8T memory cell(s).
 79. The device ofclaim 1, claim 51 or the invention of any claim herein wherein thememory cells comprises 4T memory cell(s) or 1T memory cell(s).
 80. Thedevice of claim 1, claim 51 or the invention of any claim herein,wherein the SBLs are arranged in a plurality of rows and columns. 81.The device of claim 1, claim 51 or the invention of any claim hereinfurther comprising a sense amplifier coupled to the global bit lineand/or the local bit line.
 82. The device of claim 1, claim 51 or theinvention of any claim herein further comprising a data driver coupledto the global bit line and/or the local bit line.
 83. The device ofclaim 1, claim 51 or the invention of any claim herein wherein acapacitance of the global bit line is less than a capacitance of acomparable global bit line to which the memory cell is directly coupled.84. The device of claim 1, claim 51 or the invention of any claim hereinwherein a memory cell active current is as large as an active current ofa comparable global bit line to which the memory cell is directlycoupled.
 85. The device of claim 1, claim 51 or the invention of anyclaim herein wherein an effective global bit line length is less than aneffective global bit line length of a comparable global bit line towhich the memory cell is directly coupled.
 86. A Sectioned Bit Line(SBL) of an SRAM memory device, the SBL comprising: a local bit line; amemory cell connected to the local bit line; and a pass gate coupled tothe local bit line; wherein the pass gate is configured to be coupled toa global bit line.
 87. The SBL of claim 86, wherein a drain of the passgate is coupled to the local bit line.
 88. The SBL of claim 86 whereinthe pass gate is a write pass gate defining a write path.
 89. The SBL ofclaim 88 wherein the write pass gate is an NMOS device.
 90. The SBL ofclaim 86 further comprising a read pass gate defining a read path. 91.The SBL of claim 90 wherein the read pass gate is an PMOS device. 92.The SBL of claim 86, wherein the pass gate is a write pass gate defininga write path; and further comprising: a read pass gate defining a readpath.
 93. The SBL of claim 92, wherein: the write pass gate comprises anNMOS device; and the read pass gate comprises a PMOS device.
 94. The SBLof claim 88 or claim 93, wherein the write pass gate is configured to becontrolled by a write operation signal.
 95. The SBL of claim 90 or claim93, wherein the read pass gate is configured to be controlled by a readoperation signal.
 96. The device of claim 1, claim 51 or the inventionof any claim herein wherein NMOS transistors are utilized for both theread pass gates and the write pass gates.
 97. The device of claim 1,claim 51 or the invention of any claim herein wherein PMOS transistorsare utilized for both the read pass gates and the write pass gates. 98.The device of claim 1, claim 51 or the invention of any claim hereinwherein NMOS transistors and PMOS transistors are utilized for both theread pass gates and the write pass gates.
 99. The device of claim 1claim 51 or the invention of any claim herein further comprising acomplementary pass gate cell including read pass gate circuitry, whichincludes first transistors with gates connected to the local bit lineand complement local bit line and sources coupled to drains of secondtransistors that have gates coupled to the read pass enable signal, andwrite pass gate circuitry, which includes transistors with drainscoupled to the local bit line and complement local bit line, sourcesconnected to the local data line(s) and gates connected to the writepass enable signal.
 100. An SRAM memory device comprising: a global bitline; a complement global bit line, inverse of the global bit line; asectioned bit line (SBL) comprising: a local bit line; one or morememory cells connected to the local bit line; a complement local bitline connected to the memory cell; a pass gate coupled to the local bitline; and a pass gate coupled to the complement local bit line; whereinpass gates of SBLs are configured to connect and isolate the sectionedbit line(s) and the global bit line(s).
 101. An SRAM memory devicecomprising: a global bit line; a plurality of sectioned bit lines (SBLs)each comprising: a bit line; one or more memory cells connected to thebit line; a complement bit line connected to the memory cell; and a passgate coupled to the bit line.
 102. The SRAM of claim 101 wherein passgates of the SBLs are configured to connect and/or isolate the SBLs andthe global bit line.
 103. A method of SRAM operation comprising:accessing a plurality of sectioned bit lines, the sectioned bit linesbeing sections of a global bit line, each sectioned bit line comprisinga bit line, one or more memory cells connected to the bit line, acomplement bit line connected to the memory cell, and a pass gatecoupled to the bit line; passing data/signals to or from memory cellswithin the sectioned bit line via the pass gates, wherein the pass gatesare configured to connect and isolate the sectioned bit lines and theglobal bit line.
 104. A method of SRAM operation comprising:reading/writing data to one or more of a plurality of sectioned bitlines consistent with any claim, configuration and/or aspect of thedisclosure herein.
 105. A method of operating a local section bit line(LSBL) of an SRAM comprising: accessing a plurality of sectioned bitlines, the sectioned bit lines being sections of a global bit line, eachsectioned bit line comprising a bit line, one or more memory cellsconnected to the bit line, a complement bit line connected to the memorycell, and a pass gate coupled to the bit line; and operating the passgates to connect and/or isolate the sectioned bit lines and the globalbit lines.
 106. The method of claim 105 or the invention of any claimherein, wherein the one or more memory cells comprise two or more LSBLsarranged in direction along the bit line (Y direction).
 107. The methodof claim 105 or the invention of any claim herein, wherein the one ormore memory cells comprise at least one LSBL arranged in a direction ofa word line (X direction).
 108. The method of claim 105 or the inventionof any claim herein, further comprising: operating at least one localsense amplifier and/or at least one local data driver for selection by Xand Y addresses.
 109. The method of claim 105 or the invention of anyclaim herein, further comprising: decoding multiple level columns on theglobal bit line.
 110. The method of claim 105 or the invention of anyclaim herein, further comprising: performing read/write operations usingthe global bit line, wherein the global bit line is arranged in a samedirection as the local bit line(s).
 111. The method of claim 105 or theinvention of any claim herein, further comprising: amplifying a signalon the local sense line using at least one multiple level senseamplifier, wherein the at least one multiple level sense amplifier iscoupled to at least one global bit line and/or the sectioned bit lines.112. The method of claim 105 or the invention of any claim herein,further comprising: driving data via a multiple level data driver,wherein the multiple level data driver is coupled to at least one globalbit line and/or the sectioned bit lines.
 113. The method of claim 105 orthe invention of any claim herein, further comprising: amplifying asignal on the global bit line via a single global bit line senseamplifier, wherein the single global bit line sense amplifier is coupledto one or more of the local section bit lines (LSBLs).
 114. The methodof claim 105 or the invention of any claim herein, wherein the globalbit lines, local sense amplifier enable lines, and/or local data driverenable lines are arranged on memory cells in a same direction as thelocal bit lines.
 115. The method of claim 105 or the invention of anyclaim herein, wherein a local sense amplifier enable line and/or a localdata driver enable line are arranged as Y direction decoding of theglobal bit line.
 116. The method of claim 105 or the invention of anyclaim herein, further comprising: selecting memory cells via localselect (LS) lines, wherein the LS lines are configured as a function ofX direction decoding.
 117. The method of claim 105 or the invention ofany claim herein, wherein one or more local select (LS) lines and/or oneor more local pass gate enable lines are configured in a word linedirection.
 118. A method of SRAM operation comprising the steps of:accessing a plurality of sectioned bit lines, the sectioned bit linesbeing sections of a global bit line, each sectioned bit line comprisinga bit line, one or more memory cells connected to the bit line, acomplement bit line connected to the memory cell, and a pass gatecoupled to the bit line; passing data/signals to or from memory cellswithin the sectioned bit line via the pass gates; and operating the passgates to connect and/or isolate the sectioned bit lines and the globalbit lines.
 119. The method of claim 118 further comprising emulatingdelay of the global bit line via a dummy global bit line, wherein thedummy global bit line is arranged along or in a comparable path of theglobal bit line.
 120. The method of claim 118 or the invention of anyclaim herein, wherein delay is emulated for better timing tracking. 121.The method of claim 118 or the invention of any claim herein, furthercomprising: determining an estimated delay on a global bit line viameasurement of emulated delay information on the dummy global bit line.122. The method of claim 118 or the invention of any claim herein,further comprising: performing read/write operations using the globalbit lines, wherein at least one of the global bit lines is formed in/onone or more layers above the memory cell and/or on one or more layersbelow the memory cell.
 123. The method of claim 118 or the invention ofany claim herein, further comprising: controlling operation of the SRAMvia the control signal lines, wherein at least one of the control signallines is formed on one or more layers above the memory cell and/or onone or more layers below the memory cell.
 124. An SRAM memory devicecomprising: a local section bit line including: a plurality of sectionedbit lines (SBLs), each comprising: a local bit line; one or more memorycells connected to the local bit line; a local complement bit lineconnected to the memory cell; & a pass gate coupled to the local bitline; a local shared sense amplifier; a local shared data driver; aglobal bit line; wherein the pass gates are configured to connect and/orisolate the sectioned bit line and local sense line.
 125. The device ofclaim 124 wherein the local sense amplifier is configured to amplify asignal on a local sense line and provide an output to the global bitline.
 126. An SRAM memory device comprising: a local section bit lineincluding: a plurality of sectioned bit lines (SBLs), each comprising: alocal bit line; one or more memory cells connected to the local bitline; a local complement bit line connected to the memory cell; & a passgate coupled to the local bit line; a local shared sense amplifier; alocal shared data driver; a global bit line; and a dummy global bit linethat is arranged along or in a comparable path of the global bit line;wherein the pass gates are configured to connect and/or isolate thesectioned bit line and local sense line.
 127. The device of claim 126wherein the local sense amplifier is configured to amplify a signal on alocal sense line and provide an output to the global bit line.
 128. Theinvention of any claim herein wherein one or more of: local bit linesand power buses are formed in metal 2, word lines and power buses areformed in metal 3, and/or global bit lines, control signal lines andpower buses are formed in metal
 4. 129. The invention of claim 128 orother claims herein wherein improved tracking is provided in relation tocontrol signal(s) associated with such layering/structures, such asagainst sense amplifier enable signal(s) and SBL selection signals forSRAMs.
 130. A method of SRAM operation, the method comprising:performing one or more steps of SRAM operation involving features orfunctioning of claim 1, and/or of other claims herein, and/or consistentwith one or more aspects of this disclosure.
 131. A method offabricating the SRAM device of claim 1, and/or of other claims herein,and/or consistent with one or more aspects this disclosure.
 132. Amethod of fabricating an SRAM device, the method comprising: formingtransistors onto one or more substrates; forming interconnects,including multiple metallization layers and/or interconnects between thetransistors; and connecting the transistors and/or other componentswherein an SRAM device of claim 1, and/or of other claims herein, and/orconsistent with one or more aspects of this disclosure is provided. 133.A method of fabricating an SRAM device, the method comprising: formingelements including transistors onto one or more substrates; forminginterconnects, including multiple metallization layers and/orinterconnects between the transistors, wherein one or more of: local bitlines and power buses are formed in metal 2, word lines and power busesare formed in metal 3, and/or global bit lines, control signal lines andpower buses are formed in metal 4; and connecting the transistors and/orother components wherein an SRAM device according to claim 1, and/oraccording to other claims herein, and/or consistent with one or moreaspects of this disclosure is provided.
 134. A method of fabricating anSRAM device, the method comprising: forming elements includingtransistors onto one or more substrates; forming interconnects,including multiple metallization layers and/or interconnects between thetransistors, wherein structures/layers are formed consistent with FIGS.15A-15D; and connecting the transistors and/or other components whereinan SRAM device according to claim 1, and/or according to other claimsherein, and/or consistent with one or more aspects of this disclosure isprovided.
 135. The method of any of claims 131-134 wherein thefabricating includes one or more CMOS fabrication process(es) and/orCMOS process technologies.